MRF89XA-I/MQ【PDF 79/140 页】TXRX ISM SUB-GHZ ULP 32QFN

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MRF89XA

3.10.3

INTERRUPT SIGNALS MAPPING

Table 3-8 and Table 3-9 describes the interrupts

available in Buffered mode.

TABLE 3-8:

INTERRUPT MAPPING IN BUFFERED RX AND STAND-BY MODE

Interrupt Name

Interrupts

Data Mode

Interrupt Type

RX Interrupt

Source

Stand-by Interrupt

Source

IRQ0RXS<1:0>

00 (default)

01

10

11

IRQ0

IRQ0

IRQ0

IRQ0

Buffered

Buffered

Buffered

Buffered

Output

Output

Output

Output

—

WRITEBYTE

FIFOEMPTY

Sync Pattern

—

—

FIFOEMPTY

—

IRQ1RXS<1:0>

00 (default)

01

10

IRQ1

IRQ1

IRQ1

Buffered

Buffered

Buffered

Output

Output

Output

—

FIFOFULL

RSSI

—

FIFOFULL

—

11

IRQ1

Buffered

Output

FIFO_THRESHOLD FIFO_THRESHOLD

Note:

Also refer the DMODE1 and DMODE0 bits in the FTXRXIREG and FTPRIREG registers for details.

TABLE 3-9:

INTERRUPT MAPPING IN BUFFERED TX MODE

Interrupt Name

Interrupts

Data Mode

Interrupt Type

Interrupt Source

IRQ0TXST

0 (default)

1

IRQ0

IRQ0

Buffered

Buffered

Output

Output

FIFOEMPTY

FIFOEMPTY

IRQ1TX

0 (default)

1

IRQ1

IRQ1

Buffered

Buffered

Output

Output

FIFOFULL

TXDONE

Note:

Also refer the DMODE1 and DMODE0 bits in the FTXRXIREG and FTPRIREG registers for details.

3.10.4

HOST MICROCONTROLLER

CONNECTIONS IN BUFFERED

MODE

FIGURE 3-24:

HOST MCU

CONNECTIONS IN

BUFFERED MODE

Depending on the application, some host

microcontroller connections may not be required:

? IRQ0: if none of the relevant IRQ sources are

used, leave the pin floating.

MRF89XA

IRQ0

? IRQ1: if none of the relevant IRQ sources are

used, leave the pin floating.

? SDO: if no read register access is needed and the

device is used in TX mode only. In this case, pull-

up to V DD through a 100 k ? resistor.

IRQ1

C SCON

CSDAT

SCK

SDI

PIC ?

MIcrocontroller

Note:

The DATA pin (pin 20), which is unused in

Buffered mode, should be pulled-up to

V DD through a 100 k ? resistor. Table 2-4 ,

SDO

provides details about the MRF89XA pin

configuration and chip mode.

3.10.5

BUFFERED MODE EXAMPLE

The data processing related registers are appropriately

configured as listed in Table 3-10 . In this example we

assume Sync word recognition is on and FIFOFM = 0 .

? 2010–2011 Microchip Technology Inc.

Preliminary

DS70622C-page 79

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